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| 1 p/n:pm1301 rev. 1.9, jul. 06, 2008 cmos single voltage 3v only flash memory features general features ? byte mode only: - 262,411 x8 (mx29lv002c/002nc) - 524,288 x8 (mx29lv004c) - 1,048,576 x8 (mx29lv008c) ? sector structure - 16k-byte x 1, 8k-byte x 2, 32k-byte x 1 64k-byte x 3 (mx29lv002c), 64k-byte x 7 (mx29lv004c), 64k-byte x 15 (mx29lv008c) ? sector protect - provides sector protect function to prevent program or erase operation in the protected sector - provides chip unprotect function to allow code changing - provides temporary sector unprotect function for code changing in previously protected sector ? single power supply operation - 2.7 to 3.6 volt for read, erase, and program operations ? latch-up protected to 250ma from -1v to vcc + 1v ? low vcc write inhibit : vcc 1.4v ? compatible with jedec standard - pinout and software compatible to single power supply flash performance ? high performance - fast access time: 45q (mx29lv004c only), 55q (for mx29lv004c and mx29lv008c), 70/90ns - fast program time: 9us/byte typical utilizing accelerate function - fast erase time: 0.7s/sector ? low power consumption - low active read current: 7ma (typical) at 5mhz - low standby current: 200na (typical) ? minimum 100,000 erase/program cycle ? 20 years data retention software features ? erase suspend/ erase resume - suspends sector erase operation to read data from or program data to another sector which is not being erased ? status reply - data# polling & toggle bits provide detection of program and erase operation completion ? support common flash interface (cfi) only for 29lv002c/002nc, 29lv004c hardware features ? ready/busy# (ry/by#) output only for 29lv004c, 29lv008c - provides a hardware method of detecting program and erase operation completion ? hardware reset (reset#) input - provides a hardware method to reset the internal state machine to read mode package ? 32-pin tsop (for mx29lv002c/002nc) ? 32-pin plcc (for mx29lv002c/002nc and mx29lv004c) ? 40-pin tsop (for mx29lv004c and mx29lv008c), which is not recommended for new design in ? all pb-free devices are rohs compliant mx29lv002c/002nc t/b mx29lv004c t/b mx29lv008c t/b
2 p/n:pm1301 rev. 1.9, jul. 06, 2008 mx29lv002c/002nc t/b mx29lv004c t/b mx29lv008c t/b mx29lv002c/002nc pin configurations 32 plcc 32 tsop (type 1) pin description 1 4 5 9 13 14 17 20 21 25 29 32 30 a14 a13 a8 a9 a11 oe# a10 ce# q7 a7 a6 a5 a4 a3 a2 a1 a0 q0 q1 q2 vss q3 q4 q5 q6 a12 a15 a16 reset# vcc we# a17 mx29lv002c/ 002nc t/b nc on mx29lv002nc a11 a9 a8 a13 a14 a17 we# vcc reset# a16 a15 a12 a7 a6 a5 a4 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 oe# a10 ce# q7 q6 q5 q4 q3 gnd q2 q1 q0 a0 a1 a2 a3 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 mx29lv002c/002nc t/b nc on mx29lv002nc symbol pin name a0~a17 address input q0~q7 data input/output ce# chip enable input we# write enable input reset# hardware reset pin/sector protect unlock oe# output enable input vcc power supply pin (+3v) gnd ground pin 3 p/n:pm1301 rev. 1.9, jul. 06, 2008 mx29lv002c/002nc t/b mx29lv004c t/b mx29lv008c t/b mx29lv004c pin configurations pin description 32 plcc 40 tsop (standard type) (10mm x 20mm) 1 4 5 9 13 14 17 20 21 25 29 32 30 a14 a13 a8 a9 a11 oe# a10 ce# q7 a7 a6 a5 a4 a3 a2 a1 a0 q0 q1 q2 gnd q3 q4 q5 q6 a12 a15 a16 a18 vcc we# a17 mx29lv004c t/b a16 a15 a14 a13 a12 a11 a9 a8 we# reset# nc ry/by# a18 a7 a6 a5 a4 a3 a2 a1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 a17 gnd nc nc a10 q7 q6 q5 q4 vcc vcc nc q3 q2 q1 q0 oe# vss ce# a0 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 mx29lv004c t/b symbol pin name a0~a18 address input q0~q7 data input/output ce# chip enable input we# write enable input reset# hardware reset pin/sector protect unlock (for 40-tsop) oe# output enable input ry/by# ready/busy# output (for 40-tsop) vcc power supply pin (2.7v~3.6v) gnd ground pin 4 p/n:pm1301 rev. 1.9, jul. 06, 2008 mx29lv002c/002nc t/b mx29lv004c t/b mx29lv008c t/b mx29lv008c pin configurations pin description 40 tsop (standard type) (10mm x 20mm) a16 a15 a14 a13 a12 a11 a9 a8 we# reset# nc ry/by# a18 a7 a6 a5 a4 a3 a2 a1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 a17 gnd nc a19 a10 q7 q6 q5 q4 vcc vcc nc q3 q2 q1 q0 oe# gnd ce# a0 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 mx29lv008ct/cb symbol pin name a0~a19 address input q0~q7 data input/output ce# chip enable input we# write enable input reset# hardware reset pin oe# output enable input ry/by# ready/busy output vcc power supply pin (2.7v~3.6v) gnd ground pin 5 p/n:pm1301 rev. 1.9, jul. 06, 2008 mx29lv002c/002nc t/b mx29lv004c t/b mx29lv008c t/b block diagram control input logic program/erase high voltage write state machine (wsm) state register flash array x-decoder address latch and buffer y-pass gate y-decoder array source hv command data decoder command data latch i/o buffer pgm data hv program data latch sense amplifier q0-q7 a0-am am: msb address ce# oe# we# reset# 6 p/n:pm1301 rev. 1.9, jul. 06, 2008 mx29lv002c/002nc t/b mx29lv004c t/b mx29lv008c t/b table 1. block structure mx29lv002cb sector architecture mx29lv002ct sector architecture sector sector size byte mode address range byte mode (x8) sector address a17 a16 a15 a14 a13 sa0 16kbytes 00000-03fff 0 0 0 0 x sa1 8kbytes 04000-05fff 0 0 0 1 0 sa2 8kbytes 06000-07fff 0 0 0 1 1 sa3 32kbytes 08000-0ffff 0 0 1 x x sa4 64kbytes 10000-1ffff 0 1 x x x sa5 64kbytes 20000-2ffff 1 0 x x x sa6 64kbytes 30000-3ffff 1 1 x x x sector sector size byte mode address range byte mode (x8) sector address a17 a16 a15 a14 a13 sa0 64kbytes 00000-0ffff 0 0 x x x sa1 64kbytes 10000-1ffff 0 1 x x x sa2 64kbytes 20000-2ffff 1 0 x x x sa3 32kbytes 30000-37fff 1 1 0 x x sa4 8kbytes 38000-39fff 1 1 1 0 0 sa5 8kbytes 3a000-3bfff 1 1 1 0 1 sa6 16kbytes 3c000-3ffff 1 1 1 1 x 7 p/n:pm1301 rev. 1.9, jul. 06, 2008 mx29lv002c/002nc t/b mx29lv004c t/b mx29lv008c t/b mx29lv004cb sector architecture mx29lv004ct sector architecture sector sector size byte mode address range byte mode (x8) sector address a18 a17 a16 a15 a14 a13 sa0 64kbytes 00000-0ffff 0 0 0 x x x sa1 64kbytes 10000-1ffff 0 0 1 x x x sa2 64kbytes 20000-2ffff 0 1 0 x x x sa3 64kbytes 30000-3ffff 0 1 1 x x x sa4 64kbytes 40000-4ffff 1 0 0 x x x sa5 64kbytes 50000-5ffff 1 0 1 x x x sa6 64kbytes 60000-6ffff 1 1 0 x x x sa7 32kbytes 70000-77fff 1 1 1 0 x x sa8 8kbytes 78000-79fff 1 1 1 1 0 0 sa9 8kbytes 7a000-7bfff 1 1 1 1 0 1 sa10 16kbytes 7c000-7ffff 1 1 1 1 1 x sector sector size byte mode address range byte mode (x8) sector address a18 a17 a16 a15 a14 a13 sa0 16kbytes 00000-03fff 0 0 0 0 0 x sa1 8kbytes 04000-05fff 0 0 0 0 1 0 sa2 8kbytes 06000-07fff 0 0 0 0 1 1 sa3 32kbytes 08000-0ffff 0 0 0 1 x x sa4 64kbytes 10000-1ffff 0 0 1 x x x sa5 64kbytes 20000-2ffff 0 1 0 x x x sa6 64kbytes 30000-3ffff 0 1 1 x x x sa7 64kbytes 40000-4ffff 1 0 0 x x x sa8 64kbytes 50000-5ffff 1 0 1 x x x sa9 64kbytes 60000-6ffff 1 1 0 x x x sa10 64kbytes 70000-7ffff 1 1 1 x x x 8 p/n:pm1301 rev. 1.9, jul. 06, 2008 mx29lv002c/002nc t/b mx29lv004c t/b mx29lv008c t/b mx29lv008ct sector architecture sector sector size address range sector address a19 a18 a17 a16 a15 a14 a13 sa0 64kbytes 00000h-0ffffh 0 0 0 0 x x x sa1 64kbytes 10000h-1ffffh 0 0 0 1 x x x sa2 64kbytes 20000h-2ffffh 0 0 1 0 x x x sa3 64kbytes 30000h-3ffffh 0 0 1 1 x x x sa4 64kbytes 40000h-4ffffh 0 1 0 0 x x x sa5 64kbytes 50000h-5ffffh 0 1 0 1 x x x sa6 64kbytes 60000h-6ffffh 0 1 1 0 x x x sa7 64kbytes 70000h-7ffffh 0 1 1 1 x x x sa8 64kbytes 80000h-8ffffh 1 0 0 0 x x x sa9 64kbytes 90000h-9ffffh 1 0 0 1 x x x sa10 64kbytes a0000h-affffh 1 0 1 0 x x x sa11 64kbytes b0000h-bffffh 1 0 1 1 x x x sa12 64kbytes c0000h-cffffh 1 1 0 0 x x x sa13 64kbytes d0000h-dffffh 1 1 0 1 x x x sa14 64kbytes e0000h-effffh 1 1 1 0 x x x sa15 32kbytes f0000h-f7fffh 1 1 1 1 0 x x sa16 8kbytes f8000h-f9fffh 1 1 1 1 1 0 0 sa17 8kbytes fa000h-fbfffh 1 1 1 1 1 0 1 sa18 16kbytes fc000h-fffffh 1 1 1 1 1 1 x 9 p/n:pm1301 rev. 1.9, jul. 06, 2008 mx29lv002c/002nc t/b mx29lv004c t/b mx29lv008c t/b mx29lv008cb sector architecture sector sector size address range sector address a19 a18 a17 a16 a15 a14 a13 sa0 16kbytes 00000h-03fffh 0 0 0 0 0 0 x sa1 8kbytes 04000h-05fffh 0 0 0 0 0 1 0 sa2 8kbytes 06000h-07fffh 0 0 0 0 0 1 1 sa3 32kbytes 08000h-0ffffh 0 0 0 0 1 x x sa4 64kbytes 10000h-1ffffh 0 0 0 1 x x x sa5 64kbytes 20000h-2ffffh 0 0 1 0 x x x sa6 64kbytes 30000h-3ffffh 0 0 1 1 x x x sa7 64kbytes 40000h-4ffffh 0 1 0 0 x x x sa8 64kbytes 50000h-5ffffh 0 1 0 1 x x x sa9 64kbytes 60000h-6ffffh 0 1 1 0 x x x sa10 64kbytes 70000h-7ffffh 0 1 1 1 x x x sa11 64kbytes 80000h-8ffffh 1 0 0 0 x x x sa12 64kbytes 90000h-9ffffh 1 0 0 1 x x x sa13 64kbytes a0000h-affffh 1 0 1 0 x x x sa14 64kbytes b0000h-bffffh 1 0 1 1 x x x sa15 64kbytes c0000h-cffffh 1 1 0 0 x x x sa16 64kbytes d0000h-dffffh 1 1 0 1 x x x sa17 64kbytes e0000h-effffh 1 1 1 0 x x x sa18 64kbytes f0000h-fffffh 1 1 1 1 x x x 10 p/n:pm1301 rev. 1.9, jul. 06, 2008 mx29lv002c/002nc t/b mx29lv004c t/b mx29lv008c t/b table 2. bus operation--1 note: 1. q0~q7 are input (din) or output (dout) pins according to the requests of command sequence, sector pro - tection, or data polling algorithm. mode select reset# ce# we# oe# address q0~q7 device reset l x x x x highz standby mode vcc 0.3v vcc 0.3v x x x highz output disable h l h h x highz read mode h l h l ain dout write h l l h ain din temporary sector unprotect vhv x x x ain din sector protect vhv l l h sector address, a6=l, a1=h, a0=l din chip unprotect vhv l l h sector address, a6=h, a1=h, a0=l din 11 p/n:pm1301 rev. 1.9, jul. 06, 2008 mx29lv002c/002nc t/b mx29lv004c t/b mx29lv008c t/b bus operation--2 notes: 1. sector unprotected code:00h. sector protected code:01h. 2. am: msb of address. item control input am to a13 a12 to a10 a9 a8 to a7 a6 a5 to a2 a1 a0 q0~q7 ce# we# oe# sector protect verifcation l h l sa x v hv x l x h l 01h or 00h (note1) read silicon id manufacturer code l h l x x v hv x l x l l c2h read silicon id mx29lv002ct l h l x x v hv x l x l h 59h read silicon id mx29lv002cb l h l x x v hv x l x l h 5ah read silicon id mx29lv004ct l h l x x v hv x l x l h b5h read silicon id mx29lv004cb l h l x x v hv x l x l h b6h read silicon id mx29lv008ct l h l x x v hv x l x l h 3eh read silicon id mx29lv008cb l h l x x v hv x l x l h 37h 12 p/n:pm1301 rev. 1.9, jul. 06, 2008 mx29lv002c/002nc t/b mx29lv004c t/b mx29lv008c t/b write commands/command sequences to write a command to the device, system must drive we# and ce# to vil, and oe# to vih. in a command cycle, all address are latched at the later falling edge of ce# and we#, and all data are latched at the earlier rising edge of ce# and we#. figure 1 illustrates the ac timing waveform of a write command, and table 3 defnes all the valid command sets of the device. system is not allowed to write invalid commands not defned in this datasheet. writing an invalid command will bring the device to an undefned state. requirements for reading array data read array action is to read the data stored in the array. while the memory device is in powered up or has been reset, it will automatically enter the status of read array. if the microprocessor wants to read the data stored in array, it has to drive ce# (device enable control pin) and oe# (output control pin) as vil, and input the address of the data to be read into address pin at the same time. after a period of read cycle (tce or taa), the data being read out will be displayed on output pin for microprocessor to access. if ce# or oe# is vih, the output will be in tri-state, and there will be no data displayed on output pin at all. after the memory device completes embedded operation (automatic erase or program), it will automatically re - turn to the status of read array, and the device can read the data in any address in the array. in the process of erasing, if the device receives the erase suspend command, erase operation will be stopped temporarily after a period of time no more than tready1 and the device will return to the status of read array. at this time, the device can read the data stored in any address except the sector being erased in the array. in the status of erase sus - pend, if user wants to read the data in the sectors being erased, the device will output status data onto the out - put. similarly, if program command is issued after erase suspend, after program operation is completed, system can still read array data in any address except the sectors to be erased the device needs to issue reset command to enable read array operation again in order to arbitrarily read the data in the array in the following two situations: 1. in program or erase operation, the programming or erasing failure causes q5 to go high. 2. the device is in auto select mode or cfi mode. in the two situations above, if reset command is not issued, the device is not in read array mode and system must issue reset command before reading array data. 13 p/n:pm1301 rev. 1.9, jul. 06, 2008 mx29lv002c/002nc t/b mx29lv004c t/b mx29lv008c t/b reset# operation driving reset# pin low for a period more than trp will reset the device back to read mode. if the device is in program or erase operation, the reset operation will take at most a period of tready1 for the device to return to read array mode. before the device returns to read array mode, the ry/by# pin remains low (busy status). when reset# pin is held at gnd 0.3v, the device consumes standby current(isb).however, device draws larg - er current if reset# pin is held at vil but not within gnd 0.3v. it is recommended that the system to tie its reset signal to reset# pin of fash memory, so that the fash memo - ry will be reset during system reset and allows system to read boot code from fash memory. sector protect operation when a sector is protected, program or erase operation will be disabled on that protected sector. mx29lv002c/ mx29lv004c/mx29lv008c t/b provides two methods for sector protection. once the sector is protected, the sector remains protected until next chip unprotect, or is temporarily unprotected by asserting reset# pin at vhv. refer to temporary sector unprotect operation for further details. the frst method is by applying vhv on reset# pin. refer to figure 12 for timing diagram and figure 13 for the algorithm for this method. the other method is asserting vhv on a9 and oe# pins, with a6 and ce# at vil. the protection operation begins at the falling edge of we# and terminates at the rising edge. contact macronix for details. chip unprotect operation mx29lv002c/mx29lv004c/mx29lv008c t/b provides two methods for chip unprotect. the chip unprotect operation unprotects all sectors within the device. it is recommended to protect all sectors before activating chip unprotect mode. all sector are unprotected when shipped from the factory. the frst method is by applying vhv on reset# pin. refer to figure 12 for timing diagram and figure 13 for al - gorithm of the operation. the other method is asserting vhv on a9 and oe# pins, with a6 at vih and ce# at vil (see table 2). the unpro - tect operation begins at the falling edge of we# and terminates at the rising edge. contact macronix for details. temporary sector unprotect operation system can apply reset# pin at vhv to place the device in temporary unprotect mode. in this mode, previously protected sectors can be programmed or erased just as it is unprotected. the devices returns to normal opera - tion once vhv is removed from reset# pin and previously protected sectors are again protected. 14 p/n:pm1301 rev. 1.9, jul. 06, 2008 mx29lv002c/002nc t/b mx29lv004c t/b mx29lv008c t/b automatic select operation when the device is in read array mode, erase-suspended read array mode or cfi mode, user can issue read silicon id command to enter read silicon id mode. after entering read silicon id mode, user can query several silicon ids continuously and does not need to issue read silicon id mode again. when a0 is low, device will out - put macronix manufacture id c2. when a0 is high, device will output device id. in read silicon id mode, issuing reset command will reset device back to read array mode or erase-suspended read array mode. another way to enter read silicon id is to apply high voltage on a9 pin with ce#, oe#, a6 and a1 at vil. while the high voltage of a9 pin is discharged, device will automatically leave read silicon id mode and go back to read array mode or erase-suspended read array mode. when a0 is low, device will output macronix manufacture id c2. when a0 is high, device will output device id. verify sector protect status operation mx29lv002c/mx29lv004c/mx29lv008c t/b provides hardware sector protection against program and erase operation for protected sectors. the sector protect status can be read through sector protect verify command. this method requires vhv on a9 pin, vih on we# and a1 pins, vil on ce#, oe#, a6 and a0 pins, and sector ad - dress on a13 to am pins. if the read out data is 01h, the designated sector is protected. oppositely, if the read out data is 00h, the designated sector is not protected. data protection to avoid accidental erasure or programming of the device, the device is automatically reset to read array mode during power up. besides, only after successful completion of the specifed command sets will the device begin its erase or program operation. other features to protect the data from accidental alternation are described as followed. low vcc write inhibit the device refuses to accept any write command when vcc is less than 1.4v. this prevents data from spuriously altered. the device automatically resets itself when vcc is lower than 1.4v and write cycles are ignored until vcc is greater than 1.4v. system must provide proper signals on control pins after vcc is larger than 1.4v to avoid unintentional program or erase operation write pulse "glitch" protection ce#, we#, oe# pulses shorter than 5ns are treated as glitches and will not be regarded as an effective write cycle. logical inhibit a valid write cycle requires both ce# and we# at vil with oe# at vih. write cycle is ignored when either ce# at vih, we# a vih, or oe# at vil. 15 p/n:pm1301 rev. 1.9, jul. 06, 2008 mx29lv002c/002nc t/b mx29lv004c t/b mx29lv008c t/b power-up sequence upon power up, mx29lv002c/mx29lv004c/mx29lv008c t/b is placed in read array mode. furthermore, pro - gram or erase operation will begin only after successful completion of specifed command sequences. power-up write inhibit when we#, ce# is held at vil and oe# is held at vih during power up, the device ignores the frst command on the rising edge of we#. power supply decoupling a 0.1uf capacitor should be connected between the vcc and gnd to reduce the noise effect. 16 p/n:pm1301 rev. 1.9, jul. 06, 2008 mx29lv002c/002nc t/b mx29lv004c t/b mx29lv008c t/b table 3. mx29lv002c/mx29lv004c/mx29lv008c t/b command definitions notes: 1. device id : 29lv002c: 59h/5ah (top/bottom) 29lv004c: b5h/b6h (top/bottom) 29lv008c: 3eh/37h (top/bottom) 2. for sector protect verify result, 00h means sector is not protected, 01h means sector has been protected. 3. sector protect command is valid during vhv at reset# pin, vih at a1 pin and vil at a0, a6 pins. the last bus cyc is for protect verify. 4. for mx29lv002c/002nc and mx29lv004c. 5. it is not allowed to adopt any other code which is not in the above command defnition table. command read mode reset mode automatic select program chip erase manufacturer id device id sector protect verify 1st bus cycle addr addr xxx 555 555 555 555 555 data data f0 aa aa aa aa aa 2nd bus cycle addr 2aa 2aa 2aa 2aa 2aa data 55 55 55 55 55 3rd bus cycle addr 555 555 555 555 555 data 90 90 90 a0 80 4th bus cycle addr x00 x01 (sector) x02 addr 555 data c2 id 00/01 data aa 5th bus cycle addr 2aa data 55 6th bus cycle addr 555 data 10 command sector erase erase suspend erase resume sector protect cfi (note 4) 1st bus cycle addr 555 xxx xxx xxx 55 data aa b0 30 60 98 2nd bus cycle addr 2aa sector data 55 60 3rd bus cycle addr 555 sector data 80 40 4th bus cycle addr 555 sector data aa 00/01 5th bus cycle addr 2aa data 55 6th bus cycle addr sector data 30 17 p/n:pm1301 rev. 1.9, jul. 06, 2008 mx29lv002c/002nc t/b mx29lv004c t/b mx29lv008c t/b reset in the following situations, executing reset command will reset device back to read array mode: ? among erase command sequence (before the full command set is completed) ? sector erase time-out period ? erase fail (while q5 is high) ? among program command sequence (before the full command set is completed, erase-suspended program included) ? program fail (while q5 is high, and erase-suspended program fail is included) ? read silicon id mode ? sector protect verify ? cfi mode while device is at the status of program fail or erase fail (q5 is high), user must issue reset command to reset device back to read array mode. while the device is in read silicon id mode, sector protect verify or cfi mode, user must issue reset command to reset device back to read array mode. when the device is in the progress of programming (not program fail) or erasing (not erase fail), device will ig - nore reset command. automatic select command sequence automatic select mode is used to access the manufacturer id, device id and to verify whether or not a sector is protected. the automatic select mode has four command cycles. the frst two are unlock cycles, and followed by a specifc command. the fourth cycle is a normal read cycle, and user can read at any address any number of times without entering another command sequence. the reset command is necessary to exit the automatic se - lect mode and back to read array. the following table shows the identifcation code with corresponding address. there is an alternative method to that shown in table 2, which is intended for eprom programmers and requires vhv on address bit a9. notes: device id : mx29lv002ct: 59, mx29lv002cb: 5a mx29lv004ct: b5, mx29lv004cb: b6 mx29lv008ct: 3e, mx29lv008cb: 37 address data (hex) representation manufacturer id x00 c2 device id x01 id top/bottom boot sector sector protect verify (sector address) x 02 00/01 unprotected/protected 18 p/n:pm1301 rev. 1.9, jul. 06, 2008 mx29lv002c/002nc t/b mx29lv004c t/b mx29lv008c t/b automatic programming the mx29lv002c/mx29lv004c/mx29lv008c t/b can provide the user program function by the form of byte- mode or word-mode. as long as the users enter the right cycle defned in the table.3 (including 2 unlock cycles and a0h), any data user inputs will automatically be programmed into the array. once the program function is executed, the internal write state controller will automatically execute the algo - rithms and timings necessary for program and verifcation, which includes generating suitable program pulse, verifying whether the threshold voltage of the programmed cell is high enough and repeating the program pulse if any of the cells does not pass verifcation. meanwhile, the internal control will prohibit the programming to cells that pass verifcation while the other cells fail in verifcation in order to avoid over-programming. with the internal write state controller, the device requires the user to write the program command and data only. programming will only change the bit status from "1" to "0". that is to say, it is impossible to convert the bit status from "0" to "1" by programming. meanwhile, the internal write verifcation only detects the errors of the "1" that is not successfully programmed to "0". any command written to the device during programming will be ignored except hardware reset, which will termi - nate the program operation after a period of time no more than tready1. when the embedded program algorithm is complete or the program operation is terminated by hardware reset, the device will return to the reading array data mode. when the embedded program operation is on going, user can confrm if the embedded operation is fnished or not by the following methods: *1: the status "in progress" means both program mode and erase-suspended program mode. *2: ry/by# is an open drain output pin and should be weakly connected to vcc through a pull-up resistor. *3: when an attempt is made to program a protected sector, q7 will output its complement data or q6 continues to toggle for about 1us or less and the device returns to read array state without programing the data in the pro - tected sector. status q7 q6 q5 ry/by#*2 in progress*1 q7# toggling 0 0 finished q7 stop toggling 0 1 exceed time limit q7# toggling 1 0 19 p/n:pm1301 rev. 1.9, jul. 06, 2008 mx29lv002c/002nc t/b mx29lv004c t/b mx29lv008c t/b sector erase sector erase is to erase all the data in a sector with "1" and "0" as all "1". it requires six command cycles to is - sue. the frst two cycles are "unlock cycles", the third one is a confguration cycle, the fourth and ffth are also "unlock cycles" and the sixth cycle is the sector erase command. after the sector erase command sequence is issued, there is a time-out period of 50us counted internally. during the time-out period, additional sector ad - dress and sector erase command can be written multiply. once user enters another sector erase command, the time-out period of 50us is recounted. if user enters any command other than sector eras or erase suspend dur - ing time-out period, the erase command would be aborted and the device is reset to read array condition. the number of sectors could be from one sector to all sectors. after time-out period passing by, additional erase com - mand is not accepted and erase embedded operation begins. during sector erasing, all commands will not be accepted except hardware reset and erase suspend and user can check the status as chip erase. when the embedded erase operation is on going, user can confrm if the embedded operation is fnished or not by the following methods: chip erase chip erase is to erase all the data with "1" and "0" as all "1". it needs 6 cycles to write the action in, and the frst two cycles are "unlock" cycles, the third one is a confguration cycle, the fourth and ffth are also "unlock" cycles, and the sixth cycle is the chip erase operation. during chip erasing, all the commands will not be accepted except hardware reset or the working voltage is too low that chip erase will be interrupted. after chip erase, the chip will return to the state of read array. when the embedded chip erase operation is on going, user can confrm if the embedded operation is fnished or not by the following methods: *1: the status q3 is the time-out period indicator. when q3=0, the device is in time-out period and is acceptible to another sector address to be erased. when q3=1, the device is in erase operation and only erase sus - pend is valid. *2: ry/by# is open drain output pin and should be weakly connected to vcc through a pull-up resistor. *3: when an attempt is made to erase a protected sector, q7 will output its complement data or q6 continues to toggle for 100us or less and the device returned to read array status without erasing the data in the protected sector. status q7 q6 q5 q2 ry/by# in progress 0 toggling 0 toggling 0 finished 1 stop toggling 0 1 1 exceed time limit 0 toggling 1 toggling 0 status q7 q6 q5 q3 q2 ry/by#*2 time-out period 0 toggling 0 0 toggling 0 in progress 0 toggling 0 1 toggling 0 finished 1 stop toggling 0 1 1 1 exceed time limit 0 toggling 1 1 toggling 0 20 p/n:pm1301 rev. 1.9, jul. 06, 2008 mx29lv002c/002nc t/b mx29lv004c t/b mx29lv008c t/b when the device has suspended erasing, user can execute the command sets except sector erase and chip erase, such as read silicon id, sector protect verify, program, cfi query and erase resume. sector erase resume sector erase resume command is valid only when the device is in erase suspend state. after erase resume, user can issue another erase suspend command, but there should be a 400us interval between erase resume and the next erase suspend. if user issue infnite suspend-resume loop, or suspend-resume exceeds 1024 times, the time for erasing will increase. sector erase suspend during sector erasure, sector erase suspend is the only valid command. if user issue erase suspend command in the time-out period of sector erasure, device time-out period will be over immediately and the device will go back to erase-suspended read array mode. if user issue erase suspend command during the sector erase is be - ing operated, device will suspend the ongoing erase operation, and after the tready1 (<=20us) suspend fnishes and the device will enter erase-suspended read array mode. user can judge if the device has fnished erase sus - pend through q6, q7, and ry/by#. after device has entered erase-suspended read array mode, user can read other sectors not at erase suspend by the speed of taa; while reading the sector in erase-suspend mode, device will output its status. user can use q6 and q2 to judge the sector is erasing or the erase is suspended. status q7 q6 q5 q3 q2 ry/by# erase suspend read in erase suspended sector 1 no toggle 0 n/a toggle 1 erase suspend read in non-erase suspended sector data data data data data 1 erase suspend program in non-erase suspended sector q7# toggle 0 n/a n/a 0 21 p/n:pm1301 rev. 1.9, jul. 06, 2008 mx29lv002c/002nc t/b mx29lv004c t/b mx29lv008c t/b table 4-1. cfi mode: identifcation data values (mx29lv002c/002nc and 004c only) (all values in these tables are in hexadecimal) table 4-2. cfi mode: system interface data values query command and common flash interface (cfi) mode mx29lv002c/mx29lv004c t/b features cfi mode. host system can retrieve the operating characteristics, structure and vendor-specifed information such as identifying information, memory size, byte/word confguration, operating voltages and timing information of this device by cfi mode. if the system writes the cfi query com - mand "98h", to address "55h"/"aah" (depending on word/byte mode), the device will enter the cfi query mode, any time the device is ready to read array data. the system can read cfi information at the addresses given in table 4. once user enters cfi query mode, user can not issue any other commands except reset command. the reset command is required to exit cfi mode and go back to the mode before entering cfi. the system can write the cfi query command only when the device is in read mode, erase suspend, standby mode or automatic select mode. description address (h) data (h) vcc supply minimum program/erase voltage 1b 0027 vcc supply maximum program/erase voltage 1c 0036 vpp supply minimum program/erase voltage 1d 0000 vpp supply maximum program/erase voltage 1e 0000 typical timeout per single word/byte write, 2 n us 1f 0004 typical timeout for maximum-size buffer write, 2 n us 20 0000 typical timeout per individual block erase, 2 n ms 21 000a typical timeout for full chip erase, 2 n ms 22 0000 maximum timeout for word/byte write, 2 n times typical 23 0005 maximum timeout for buffer write, 2 n times typical 24 0000 maximum timeout per individual block erase, 2 n times typical 25 0004 maximum timeout for chip erase, 2 n times typical 26 0000 description address (h) data (h) query-unique ascii string "qry" 10 0051 11 0052 12 0059 primary vendor command set and control interface id code 13 0002 14 0000 address for primary algorithm extended query table 15 0040 16 0000 alternate vendor command set and control interface id code 17 0000 18 0000 address for alternate algorithm extended query table 19 0000 1a 0000 22 p/n:pm1301 rev. 1.9, jul. 06, 2008 mx29lv002c/002nc t/b mx29lv004c t/b mx29lv008c t/b table 4-3. cfi mode: device geometry data values description address (h) data (h) device size = 2 n in number of bytes (mx29lv002c) device size = 2 n in number of bytes (mx29lv004c) 27 0012 27 0013 flash device interface description 28 0000 29 0000 maximum number of bytes in buffer write = 2 n (not support) 2a 0000 2b 0000 number of erase regions within device 2c 0004 index for erase bank area 1 [2e,2d] = # of same-size sectors in region 1-1 [30, 2f] = sector size in multiples of 256-bytes 2d 0000 2e 0000 2f 0040 30 0000 index for erase bank area 2 31 0001 32 0000 33 0020 34 0000 index for erase bank area 3 35 0000 36 0000 37 0080 38 0000 index for erase bank area 4 (for mx29lv002c) index for erase bank area 4 (for mx29lv004c) 39 0002 39 0006 3a 0000 3b 0000 3c 0001 23 p/n:pm1301 rev. 1.9, jul. 06, 2008 mx29lv002c/002nc t/b mx29lv004c t/b mx29lv008c t/b table 4-4. cfi mode: primary vendor-specifc extended query data values description address (h) data (h) query - primary extended table, unique ascii string, pri 40 0050 41 0052 42 0049 major version number, ascii 43 0031 minor version number, ascii 44 0030 unlock recognizes address (0= recognize, 1= don't recognize) 45 0000 erase suspend (2= to both read and program) 46 0002 sector protect (n= # of sectors/group) 47 0001 temporary sector unprotect (1=supported) 48 0001 sector protect/chip unprotect scheme 49 0004 simultaneous r/w operation (0=not supported) 4a 0000 burst mode (0=not supported) 4b 0000 page mode (0=not supported) 4c 0000 24 p/n:pm1301 rev. 1.9, jul. 06, 2008 mx29lv002c/002nc t/b mx29lv004c t/b mx29lv008c t/b absolute maximum stress ratings operating temperature and voltage commercial (c) grade surrounding temperature (t a ) 0c to +70c industrial (i) grade surrounding temperature (t a ) -40c to +85c vcc supply voltages full vcc range +2.7 v to 3.6 v regulated vcc voltage range +3.0 v to 3.6 v surrounding temperature with bias -65 o c to +125 o c storage temperature -65 o c to +150 o c voltage range vcc -0.5v to +4.0 v reset#, a9 and oe# -0.5v to +12.5v the other pins -0.5v to vcc +0.5v output short circuit current (less than one second) 200 ma 25 p/n:pm1301 rev. 1.9, jul. 06, 2008 mx29lv002c/002nc t/b mx29lv004c t/b mx29lv008c t/b dc characteristics symbol description min typ max remark iilk input leak 1.0ua iilk9 a9 leak 35ua a9=12.5v iolk output leak 1.0ua icr1 read current (5mhz) 7ma 12ma ce#=vil, oe#=vih icr2 read current (1mhz) 2ma 4ma ce#=vil, oe#=vih icw write current 15ma 30ma ce#=vil, oe#=vih, we#=vil isb standby current 0.2ua 5ua vcc=vcc max, other pin disable isbr reset current 0.2ua 5ua vcc=vccmax, reset# enable, other pin disable isbs sleep mode current 0.2ua 5ua vil input low voltage -0.5v 0.8v vih input high voltage 0.7xvcc vcc+0.3v vhv very high voltage for hardware protect/ unprotect/auto select/temporary unprotect 11.5v 12.5v vol output low voltage 0.45v iol=4.0ma voh1 ouput high voltage 0.85xvcc ioh1=-2ma voh2 ouput high voltage vcc-0.4v ioh2=-100ua 26 p/n:pm1301 rev. 1.9, jul. 06, 2008 mx29lv002c/002nc t/b mx29lv004c t/b mx29lv008c t/b switching test circuits test condition output load : 1 ttl gate output load capacitance,cl : 30pf(45q/55q/70ns)/100pf(90ns) rise/fall times : 5ns in/out reference levels :1.5v switching test waveforms 1.5v 1.5v test points 3.0v 0.0v output input r1=6.2k ohm r2=2.7k ohm tested device diodes=in3064 or equivalent cl r1 vcc 0.1uf r2 +3.3v 27 p/n:pm1301 rev. 1.9, jul. 06, 2008 mx29lv002c/002nc t/b mx29lv004c t/b mx29lv008c t/b ac characteristics mx29lv002c/002nc symbol description min typ max unit taa valid data output after address 70/90 ns tce valid data output after ce# low 70/90 ns toe valid data output after oe# low 30/35 ns tdf data output foating after oe# high 25/30 ns toh output hold time from the earliest rising edge of address, ce#, oe# 0 ns trc read period time 70/90 ns twc write period time 70/90 ns tcwc command write period time 70/90 ns tas address setup time 0 ns tah address hold time 45 ns tds data setup time 35/45 ns tdh data hold time 0 ns tvcs vcc setup time 50 us tcs chip enable setup time 0 ns tch chip enable hold time 0 ns toes output enable setup time 0 ns toeh output enable hold time read 0 ns to g g l e & d a t a # polling 10 ns tws we# setup time 0 ns twh we# hold time 0 ns tcep ce# pulse width 35 ns tceph ce# pulse width high 30 ns twp we# pulse width 35 ns twph we# pulse width high 30 ns tbusy program/erase active time by ry/by# 90 ns tghwl read recover time before write 0 ns tghel read recover time before write (ce# control) 0 ns twhwh1 byte program operation 9 300 us twhwh2 sector erase operation 0.7 8 sec tbal sector add hold time 50 us 28 p/n:pm1301 rev. 1.9, jul. 06, 2008 mx29lv002c/002nc t/b mx29lv004c t/b mx29lv008c t/b mx29lv004c (restricated vcc=3.0v~3.6v for 45r/55r) notes: only 40-tsop provide ry/by# pin. symbol description min typ max unit taa valid data output after address 45/55/70/90 ns tce valid data output after ce# low 45/55/70/90 ns toe valid data output after oe# low 30/30/30/35 ns tdf data output foating after oe# high 25/25/25/30 ns toh output hold time from the earliest rising edge of address, ce#, oe# 0 ns trc read period time 45/55/70/90 ns twc write period time 70/90 ns tcwc command write period time 70/90 ns tas address setup time 0 ns tah address hold time 45 ns tds data setup time 35/45 ns tdh data hold time 0 ns tvcs vcc setup time 50 us tcs chip enable setup time 0 ns tch chip enable hold time 0 ns toes output enable setup time 0 ns toeh output enable hold time read 0 ns toggle & data# polling 10 ns tws we# setup time 0 ns twh we# hold time 0 ns tcep ce# pulse width 35 ns tceph ce# pulse width high 30 ns twp we# pulse width 35 ns twph we# pulse width high 30 ns tbusy program/erase active time by ry/by# 90 ns tghwl read recover time before write 0 ns tghel read recover time before write (ce# control) 0 ns twhwh1 byte program operation 9 300 us twhwh2 sector erase operation 0.7 8 sec tbal sector add hold time 50 us 29 p/n:pm1301 rev. 1.9, jul. 06, 2008 mx29lv002c/002nc t/b mx29lv004c t/b mx29lv008c t/b mx29lv008c (restricated vcc=3.0v~3.6v for 55r) symbol description min typ max unit taa valid data output after address 55/70/90 ns tce valid data output after ce# low 55/70/90 ns toe valid data output after oe# low 30/30/35 ns tdf data output foating after oe# high 25/25/30 ns toh output hold time from the earliest rising edge of address, ce#, oe# 0 ns trc read period time 55/70/90 ns twc write period time 70/90 ns tcwc command write period time 70/90 ns tas address setup time 0 ns tah address hold time 45 ns tds data setup time 35/45 ns tdh data hold time 0 ns tvcs vcc setup time 50 us tcs chip enable setup time 0 ns tch chip enable hold time 0 ns toes output enable setup time 0 ns toeh output enable hold time read 0 ns toggle & data# polling 10 ns tws we# setup time 0 ns twh we# hold time 0 ns tcep ce# pulse width 35 ns tceph ce# pulse width high 30 ns twp we# pulse width 35 ns twph we# pulse width high 30 ns tbusy program/erase active time by ry/by# 90 ns tghwl read recover time before write 0 ns tghel read recover time before write (ce# control) 0 ns twhwh1 byte program operation 9 300 us twhwh2 sector erase operation 0.7 8 sec tbal sector add hold time 50 us 30 p/n:pm1301 rev. 1.9, jul. 06, 2008 mx29lv002c/002nc t/b mx29lv004c t/b mx29lv008c t/b figure 1. command write operation addresses ce# oe# we# din tds ta h data tdh tcs tch tcwc twph twp toes ta s vih vil vih vil vih vil vih vil vih vil va va: valid address 31 p/n:pm1301 rev. 1.9, jul. 06, 2008 mx29lv002c/002nc t/b mx29lv004c t/b mx29lv008c t/b read/reset operation figure 2. read timing waveforms addresses ce# oe# ta a we# vih vil vih vil vih vil vih vil voh vol high z high z data valid to e toeh tdf tce trc outputs to h add valid 32 p/n:pm1301 rev. 1.9, jul. 06, 2008 mx29lv002c/002nc t/b mx29lv004c t/b mx29lv008c t/b figure 3. reset# timing waveform ac characteristics trh trb1 trp2 trp1 tready2 tready1 ry/by# ce#, oe# reset# reset timing not during automatic algorithms reset timing during automatic algorithms ry/by# ce#, oe# trb2 we# reset# item description setup speed unit trp1 reset# pulse width (during automatic algorithms) min 500 ns trp2 reset# pulse width (not during automatic algorithms) min 500 ns trh reset# high time before read min 50 ns trb1 ry/by# recovery time (to ce#, oe# go low) min 0 ns trb2 ry/by# recovery time (to we# go low) min 50 ns tready1 reset# pin low (during automatic algorithms) to read or write algorithms) to read or write max 20 us tready2 reset# pin low (not during automatic max 500 ns 33 p/n:pm1301 rev. 1.9, jul. 06, 2008 mx29lv002c/002nc t/b mx29lv004c t/b mx29lv008c t/b erase/program operation figure 4. automatic chip erase timing waveform twc address oe# ce# 55h 2aah sa 10h in progress complete va va ta s ta h sa: 555h for chip erase tghwl tch twp tds tdh read status last 2 erase command cycle tbusy trb tcs twph we# data ry/by# 34 p/n:pm1301 rev. 1.9, jul. 06, 2008 mx29lv002c/002nc t/b mx29lv004c t/b mx29lv008c t/b figure 5. automatic chip erase algorithm flowchart start write data aah address 555h write data 55h address 2aah write data aah address 555h write data 80h address 555h yes no data=ffh ? write data 10h address 555h write data 55h address 2aah data# polling algorithm or toggle bit algorithm auto chip erase completed 35 p/n:pm1301 rev. 1.9, jul. 06, 2008 mx29lv002c/002nc t/b mx29lv004c t/b mx29lv008c t/b figure 6. automatic sector erase timing waveform twc address oe# ce# 55h 2aah sector address 1 sector address 0 30h in progress complete va va 30h sector address n ta s ta h tbal tghwl tch twp tds tdh twhwh2 read status last 2 erase command cycle tbusy trb tcs twph we# data ry/by# 30h 36 p/n:pm1301 rev. 1.9, jul. 06, 2008 mx29lv002c/002nc t/b mx29lv004c t/b mx29lv008c t/b figure 7. automatic sector erase algorithm flowchart start write data aah address 555h write data 55h address 2aah write data aah address 555h write data 80h address 555h write data 30h sector address write data 55h address 2aah data# polling algorithm or toggle bit algorithm auto sector erase completed no last sector to erase yes yes no data=ffh 37 p/n:pm1301 rev. 1.9, jul. 06, 2008 mx29lv002c/002nc t/b mx29lv004c t/b mx29lv008c t/b figure 8. erase suspend/resume flowchart start write data b0h toggle bit checking q6 not toggled erase suspend yes no write data 30h continue erase reading or programming end read array or program another erase suspend ? no yes yes no erase resume 38 p/n:pm1301 rev. 1.9, jul. 06, 2008 mx29lv002c/002nc t/b mx29lv004c t/b mx29lv008c t/b figure 9. automatic program timing waveforms address oe# ce# a0h 555h pa pd status dout va va ta s ta h tghwl tch twp tds tdh twhwh1 last 2 read status cycle last 2 program command cycle tbusy trb tcs twph we# data ry/by# 39 p/n:pm1301 rev. 1.9, jul. 06, 2008 mx29lv002c/002nc t/b mx29lv004c t/b mx29lv008c t/b figure 10. ce# controlled write timing waveform address oe# ce# a0h 555h pa pd status dout va va ta s ta h tghwl tcep tds tdh twhwh1 or twhwh2 tbusy tceph we# data ry/by# 40 p/n:pm1301 rev. 1.9, jul. 06, 2008 mx29lv002c/002nc t/b mx29lv004c t/b mx29lv008c t/b figure 11. automatic programming algorithm flowchart start write data aah address 555h write data 55h address 2aah write program data/address write data a0h address 555h yes read again data: program data? yes auto program completed data# polling algorithm or toggle bit algorithm next address last word to be programed no no 41 p/n:pm1301 rev. 1.9, jul. 06, 2008 mx29lv002c/002nc t/b mx29lv004c t/b mx29lv008c t/b sector protect/chip unprotect figure 12. sector protect/chip unprotect waveform (reset# control) 150us: sector protect 15ms: chip unprotect 1us vhv vih data sa, a6 a1, a0 ce# we# oe# va va va status va: valid address 40h 60h 60h verification reset# 42 p/n:pm1301 rev. 1.9, jul. 06, 2008 mx29lv002c/002nc t/b mx29lv004c t/b mx29lv008c t/b figure 13-1. in-system sector protect with reset#=vhv start retry count=0 reset#=vhv wait 1us write sector address with [a6,a1,a0]:[0,1,0] data: 60h write sector address with [a6,a1,a0]:[0,1,0] data: 40h read at sector address with [a6,a1,a0]:[0,1,0] wait 150us reset plscnt=1 temporary unprotect mode reset#=vih write reset cmd sector protect done device fail temporary unprotect mode retry count +1 first cmd=60h? data=01h? retry count=25? yes yes yes yes no no no no protect another sector? 43 p/n:pm1301 rev. 1.9, jul. 06, 2008 mx29lv002c/002nc t/b mx29lv004c t/b mx29lv008c t/b figure 13-2. chip unprotect algorithms with reset#=vhv write [a6,a1,a0]:[1,1,0] data: 60h write [a6,a1,a0]:[1,1,0] data: 40h read [a6,a1,a0]:[1,1,0] wait 15ms temporary unprotect write reset cmd chip unprotect done retry count +1 device fail all sectors protected? data=00h? retry count=1000? yes yes no no yes protect all sectors start retry count=0 reset#=vhv wait 1us temporary unprotect first cmd=60h? yes no no 44 p/n:pm1301 rev. 1.9, jul. 06, 2008 mx29lv002c/002nc t/b mx29lv004c t/b mx29lv008c t/b figure 14. sector protect timing waveform (a9, oe# control) notes: tvlht (voltage transition time)=4us min. twpp1 (write pulse width for sector protect)=100ns min, 10us(typ.) twpp2 (write pulse width for chip unprotected)=100ns min, 12ms(typ.) toesp (oe# setup time to we# active)=4us min. to e data oe# we# 12v 3v 12v 3v ce# a9 a1 a6 toesp twpp1 tvlht tvlht tvlht verify 01h f0h am-a13 sector address 45 p/n:pm1301 rev. 1.9, jul. 06, 2008 mx29lv002c/002nc t/b mx29lv004c t/b mx29lv008c t/b figure 15. sector protection algorithm (a9, oe# control) start write sector addr retry count=0 retry count+1 sector protect done data=01h? yes . oe#=vhv, a9=vhv, ce#=vil a6=vil activate we# pulse time out 150us we#=vih, ce#=oe#=vil a9=vhv read at sector address with a1=1 protect another sector? remove vhv from a9 write reset command device failed plscnt=32? yes no no 46 p/n:pm1301 rev. 1.9, jul. 06, 2008 mx29lv002c/002nc t/b mx29lv004c t/b mx29lv008c t/b figure 16. timing waveform for chip unprotection (a9, oe# control) notes: tvlht (voltage transition time)=4us min. twpp1 (write pulse width for sector protect)=100ns min, 10us(typ.) twpp2 (write pulse width for chip unprotected)=100ns min, 12ms(typ.) toesp (oe# setup time to we# active)=4us min. to e data we# 12v vcc ce# a9 a1 toesp twpp2 oe# 12v vcc tvlht tvlht verify 00h a6 sector address am-a13 f0h tvlht 47 p/n:pm1301 rev. 1.9, jul. 06, 2008 mx29lv002c/002nc t/b mx29lv004c t/b mx29lv008c t/b figure 17. chip unprotection algorithm (a9, oe# control) start protect all sectors retry count=0 chip unprotect done data=00h? yes oe#=a9=vhv ce#=vil, a6=vih activate we# pulse time out 50ms sector protect verify from first sector with ce#=oe#=vil, a9=vhv, a1=1 all sectors have been verified? remove vhv from a9 write reset command device failed plscnt=1000? no retry count +1 no yes yes no go to next sector * before chip unprotect, all sectors should be protected. 48 p/n:pm1301 rev. 1.9, jul. 06, 2008 mx29lv002c/002nc t/b mx29lv004c t/b mx29lv008c t/b figure 18. temporary sector unprotect waveforms table 5. temporary sector unprotect reset# ce# we# ry/by# trpvhh 12v vhv 0 or vih vil or vih tvhhwl trpvhh program or erase command sequence parameter alt description condition speed unit trpvhh tvidr reset# rise time to vhv and vhv fall time to reset# min 500 ns tvhhwl trsp reset# vhv to we# low min 4 us 49 p/n:pm1301 rev. 1.9, jul. 06, 2008 mx29lv002c/002nc t/b mx29lv004c t/b mx29lv008c t/b figure 19. temporary sector unprotect flowchart notes: 1. temporary unprotect all protected sectors vhv=11.5~12.5v. 2. the protected conditions of the protected sectors are the same to temporary sector unprotect mode. start apply reset# pin vhv volt enter program or erase mode (1) remove vhv volt from reset# (2) reset# = vih completed temporary sector unprotected mode mode operation completed 50 p/n:pm1301 rev. 1.9, jul. 06, 2008 mx29lv002c/002nc t/b mx29lv004c t/b mx29lv008c t/b figure 20. silicon id read timing waveform ta a tce ta a to e to h to h tdf data out c2h device id vhv vih vil a9 add ce# a1 oe# we# a0 data out data q0-q7 vih vil vih vil vih vil vih vil vih vil vih vil vih vil notes: device id : mx29lv002ct: 59, mx29lv002cb: 5a mx29lv004ct: b5, mx29lv004cb: b6 mx29lv008ct: 3e, mx29lv008cb: 37 51 p/n:pm1301 rev. 1.9, jul. 06, 2008 mx29lv002c/002nc t/b mx29lv004c t/b mx29lv008c t/b write operation status figure 21. data# polling timing waveforms (during automatic algorithms) tdf tce tch to e toeh to h ce# oe# we# q7 q0-q6 ry/by# tbusy status data status data complement complement true valid data ta a trc address va va high z high z valid data true 52 p/n:pm1301 rev. 1.9, jul. 06, 2008 mx29lv002c/002nc t/b mx29lv004c t/b mx29lv008c t/b figure 22. data# polling algorithm read q7~q0 at valid address (note 1) read q7~q0 at valid address start q7 = data# ? q5 = 1 ? q7 = data# ? (note 2) fail pass no no no ye s ye s ye s notes: 1. for programming, valid address means program address. for erasing, valid address means erase sectors address. 2. q7 should be rechecked even q5="1" because q7 may change simultaneously with q5. 53 p/n:pm1301 rev. 1.9, jul. 06, 2008 mx29lv002c/002nc t/b mx29lv004c t/b mx29lv008c t/b figure 23. toggle bit timing waveforms (during automatic algorithms) tdf tce tch to e toeh ta a trc to h address ce# oe# we# q6/q2 ry/by# tbusy valid status (first read) valid status (second read) (stops toggling) valid data va va va va : valid address va valid data 54 p/n:pm1301 rev. 1.9, jul. 06, 2008 mx29lv002c/002nc t/b mx29lv004c t/b mx29lv008c t/b figure 24. toggle bit algorithm notes: 1. read toggle bit twice to determine whether or not it is toggling. 2. recheck toggle bit because it may stop toggling as q5 changes to "1". read q7-q0 twice q5 = 1? read q7~q0 twice pgm/ers fail write reset cmd pgm/ers complete q6 toggle ? q6 toggle ? no (note 1) yes no no yes yes start 55 p/n:pm1301 rev. 1.9, jul. 06, 2008 mx29lv002c/002nc t/b mx29lv004c t/b mx29lv008c t/b recommended operating conditions at device power-up ac timing illustrated in figure a is recommended for the supply voltages and the control signals at device power- up. if the timing in the fgure is ignored, the device may not operate correctly. figure a. ac timing at device power-up vcc address ce# we# oe# data tvr taa tr or tf tr or tf tce tf vcc(min) gnd vih vil vih vil vih vil vih vil vih vil voh high z vol wp#/acc valid ouput valid address tvcs tr toe tf tr symbol parameter min. max. unit tvr vcc rise time 20 500000 us/v tr input signal rise time 20 us/v tf input signal fall time 20 us/v 56 p/n:pm1301 rev. 1.9, jul. 06, 2008 mx29lv002c/002nc t/b mx29lv004c t/b mx29lv008c t/b latch-up characteristics erase and programming performance tsop/plcc pin capacitance parameter limits units min. typ. max. chip erase time mx29lv002c 2.5 16 sec mx29lv004c 4 32 sec mx29lv008c 8 32 sec sector erase time 0.7 8 sec erase/program cycles 100,000 cycles chip programming time mx29lv002c 3.0 7 sec mx29lv004c 4.5 13.5 sec mx29lv008c 9 27 sec byte programming time 9 300 us data retention parameter condition min. max. unit data retention 55?c 20 years min. max. input voltage voltage difference with gnd on all pins except i/o pins -1.0v 12.5v input voltage voltage difference with gnd on all i/o pins -1.0v vcc + 1.0v vcc current -100ma +100ma all pins included except vcc. test conditions: vcc = 3.0v, one pin per testing parameter symbol parameter description test set typ max unit cin2 control pin capacitance vin=0 12 pf cout output capacitance vout=0 12 pf cin input capacitance vin=0 8 pf 57 p/n:pm1301 rev. 1.9, jul. 06, 2008 mx29lv002c/002nc t/b mx29lv004c t/b mx29lv008c t/b ordering information mx29lv002c part no. access time (ns) operating current max. (ma) standby current max. (ua) package remark mx29lv002cttc-70g 70 30 5 32 pin tsop pb free mx29lv002cttc-90g 90 30 5 32 pin tsop pb free mx29lv002cbtc-70g 70 30 5 32 pin tsop pb free mx29lv002cbtc-90g 90 30 5 32 pin tsop pb free mx29lv002ctti-70g 70 30 5 32 pin tsop pb free mx29lv002ctti-90g 90 30 5 32 pin tsop pb free mx29lv002cbti-70g 70 30 5 32 pin tsop pb free mx29lv002cbti-90g 90 30 5 32 pin tsop pb free mx29lv002ctqc-70g 70 30 5 32 pin plcc pb free mx29lv002ctqc-90g 90 30 5 32 pin plcc pb free mx29lv002cbqc-70g 70 30 5 32 pin plcc pb free mx29lv002cbqc-90g 90 30 5 32 pin plcc pb free mx29lv002ctqi-70g 70 30 5 32 pin plcc pb free mx29lv002ctqi-90g 90 30 5 32 pin plcc pb free mx29lv002cbqi-70g 70 30 5 32 pin plcc pb free mx29lv002cbqi-90g 90 30 5 32 pin plcc pb free 58 p/n:pm1301 rev. 1.9, jul. 06, 2008 mx29lv002c/002nc t/b mx29lv004c t/b mx29lv008c t/b mx29lv002nc part no. access time (ns) operating current max. (ma) standby current max. (ua) package remark mx29lv002ncttc-70g 70 30 5 32 pin tsop pb free mx29lv002ncttc-90g 90 30 5 32 pin tsop pb free mx29lv002ncbtc-70g 70 30 5 32 pin tsop pb free mx29lv002ncbtc-90g 90 30 5 32 pin tsop pb free mx29lv002nctti-70g 70 30 5 32 pin tsop pb free mx29lv002nctti-90g 90 30 5 32 pin tsop pb free mx29lv002ncbti-70g 70 30 5 32 pin tsop pb free mx29lv002ncbti-90g 90 30 5 32 pin tsop pb free mx29lv002nctqc-70g 70 30 5 32 pin plcc pb free mx29lv002nctqc-90g 90 30 5 32 pin plcc pb free mx29lv002ncbqc-70g 70 30 5 32 pin plcc pb free mx29lv002ncbqc-90g 90 30 5 32 pin plcc pb free mx29lv002nctqi-70g 70 30 5 32 pin plcc pb free mx29lv002nctqi-90g 90 30 5 32 pin plcc pb free mx29lv002ncbqi-70g 70 30 5 32 pin plcc pb free mx29lv002ncbqi-90g 90 30 5 32 pin plcc pb free 59 p/n:pm1301 rev. 1.9, jul. 06, 2008 mx29lv002c/002nc t/b mx29lv004c t/b mx29lv008c t/b mx29lv004c * 40-tsop is not recommended for new design in. part no. access time (ns) operating current max. (ma) standby current max. (ua) package remark mx29lv004cttc-55q 55 30 5 40 pin tsop pb free mx29lv004cbtc-55q 55 30 5 40 pin tsop pb free mx29lv004cttc-70g 70 30 5 40 pin tsop pb free mx29lv004cbtc-70g 70 30 5 40 pin tsop pb free mx29lv004cttc-90g 90 30 5 40 pin tsop pb free mx29lv004cbtc-90g 90 30 5 40 pin tsop pb free mx29lv004ctti-55q 55 30 5 40 pin tsop pb free MX29LV004CBTI-55Q 55 30 5 40 pin tsop pb free mx29lv004ctti-70g 70 30 5 40 pin tsop pb free mx29lv004cbti-70g 70 30 5 40 pin tsop pb free mx29lv004ctti-90g 90 30 5 40 pin tsop pb free mx29lv004cbti-90g 90 30 5 40 pin tsop pb free mx29lv004ctqc-55q 55 30 5 32 pin plcc pb free mx29lv004cbqc-55q 55 30 5 32 pin plcc pb free mx29lv004ctqc-70g 70 30 5 32 pin plcc pb free mx29lv004cbqc-70g 70 30 5 32 pin plcc pb free mx29lv004ctqc-90g 90 30 5 32 pin plcc pb free mx29lv004cbqc-90g 90 30 5 32 pin plcc pb free mx29lv004ctqi-55q 55 30 5 32 pin plcc pb free mx29lv004cbqi-55q 55 30 5 32 pin plcc pb free mx29lv004ctqi-70g 70 30 5 32 pin plcc pb free mx29lv004cbqi-70g 70 30 5 32 pin plcc pb free mx29lv004ctqi-90g 90 30 5 32 pin plcc pb free mx29lv004cbqi-90g 90 30 5 32 pin plcc pb free mx29lv004ctti-45q 45 30 5 40 pin tsop pb free mx29lv004cbti-45q 45 30 5 40 pin tsop pb free 60 p/n:pm1301 rev. 1.9, jul. 06, 2008 mx29lv002c/002nc t/b mx29lv004c t/b mx29lv008c t/b mx29lv008c * 40-tsop is not recommended for new design in. part no. access time (ns) operating current max. (ma) standby current max. (ua) package remark mx29lv008cttc-55q 55 30 5 40 pin tsop pb-free mx29lv008cttc-70g 70 30 5 40 pin tsop pb-free mx29lv008cttc-90g 90 30 5 40 pin tsop pb-free mx29lv008cbtc-55q 55 30 5 40 pin tsop pb-free mx29lv008cbtc-70g 70 30 5 40 pin tsop pb-free mx29lv008cbtc-90g 90 30 5 40 pin tsop pb-free mx29lv008ctti-55q 55 30 5 40 pin tsop pb-free mx29lv008ctti-70g 70 30 5 40 pin tsop pb-free mx29lv008ctti-90g 90 30 5 40 pin tsop pb-free mx29lv008cbti-55q 55 30 5 40 pin tsop pb-free mx29lv008cbti-70g 70 30 5 40 pin tsop pb-free mx29lv008cbti-90g 90 30 5 40 pin tsop pb-free 61 p/n:pm1301 rev. 1.9, jul. 06, 2008 mx29lv002c/002nc t/b mx29lv004c t/b mx29lv008c t/b part name description mx 29 l v 70 c t t c g option: g: lead-free pac kage q: restr icted vcc (3.0v~3.6v) with lead-free pac kage speed: 45: 45ns 55: 55ns 70: 70ns 90: 90ns temper a ture range : c: commercial ( 0 c to 70 c) i: industr ial (-40 c to 85 c) p a ck a ge: q: plcc t : tsop boo t block type : t : t op boot b: bottom boot revision : c density & mode : 002/002n : 2mb , x8 boot bloc k 004: 4mb , x8 boot bloc k 008: 8mb , x8 boot bloc k type : l v : 3v device : 29:flash 002 62 p/n:pm1301 rev. 1.9, jul. 06, 2008 mx29lv002c/002nc t/b mx29lv004c t/b mx29lv008c t/b package information 63 p/n:pm1301 rev. 1.9, jul. 06, 2008 mx29lv002c/002nc t/b mx29lv004c t/b mx29lv008c t/b 64 p/n:pm1301 rev. 1.9, jul. 06, 2008 mx29lv002c/002nc t/b mx29lv004c t/b mx29lv008c t/b 65 p/n:pm1301 rev. 1.9, jul. 06, 2008 mx29lv002c/002nc t/b mx29lv004c t/b mx29lv008c t/b revision history revision no. description page date 1.1 1. corrected wrong cfi address data p21~23 aug/25/2006 1.2 1. added statement p67 nov/06/2006 1.3 1. correct typo p16,18,19, dec/12/2007 p42,52 1.4 1. revised statement p21 dec/28/2007 1.5 1. added note 5 into table 3. command defnitions p16 jan/17/2008 1.6 1. modifed figure 10. ce# controlled write timing waveform p39 feb/21/2008 1.7 1. modifed erase and programming performance table p56 jul/31/2008 2. 40-tsop is not recommended for new design in p1,59,60 3. revised twc, tcwc, tds timing spec p28 4. removed non pb-free part no. p57~61 1.8 1. modifed wrong sector architecture of mx29lv002ct p6 oct/21/2008 1.9 1. added data retention table p56 jul/06/2009 2. changed data retention from 10-years to 20-years p1 2. modifed the sector erase time max from 15s to 8s p27~29,56 mx29lv002c/002nc t/b mx29lv004c t/b mx29lv008c t/b 66 m acronix i nternational c o., l td. macronix offces : taiwan headquarters, fab2 macronix, international co., ltd. 16, li-hsin road, science park, hsinchu, taiwan, r.o.c. tel: +886-3-5786688 fax: +886-3-5632888 taipei offce macronix, international co., ltd. 19f, 4, min-chuan e. road, sec. 3, taipei, taiwan, r.o.c. tel: +886-2-2509-3300 fax: +886-2-2509-2200 macronix offces : china macronix (hong kong) co., limited. 702-703, 7/f, building 9, hong kong science park, 5 science park west avenue, sha tin, n.t. tel: +86-852-2607-4289 fax: +86-852-2607-4229 macronix (hong kong) co., limited, suzhou offce no.5, xinghai rd, suzhou industrial park, suzhou china 215021 tel: +86-512-62580888 ext: 3300 fax: +86-512-62586799 macronix (hong kong) co., limited, shenzhen offce room 1401 & 1404, block a, tianan hi-tech plaza tower, che gong miao, futiandistrict, shenzhen prc 518040 tel: +86-755-83433579 fax: +86-755-83438078 http : //www.macronix.com macronix international co., ltd. reserves the right to change product and specifcations without notice. macronix's products are not designed, manufactured, or intended for use for any high risk applications in which the failure of a single component could cause death, personal injury, severe physical damage, or other substantial harm to persons or property, such as life-support systems, high temperature automotive, medical, aircraft and military ap - plication. macronix and its suppliers will not be liable to you and/or any third party for any claims, injuries or damages that may be incurred due to use of macronix's products in the prohibited applications. copyright ? macronix international co., ltd. 2004~2009. all rights reserved. macronix, mxic, mxic logo, mx logo, are trademarks or registered trademarks of macronix international co., ltd.. the names and brands of other companies are for identifcation purposes only and may be claimed as the property of the respective companies. macronix offces : japan macronix asia limited. nkf bldg. 5f, 1-2 higashida-cho, kawasaki-ku kawasaki-shi, kanagawa pref. 210-0005, japan tel: +81-44-246-9100 fax: +81-44-246-9105 macronix offces : korea macronix asia limited. #906, 9f, kangnam bldg., 1321-4, seocho-dong, seocho-ku, 135-070, seoul, korea tel: +82-02-588-6887 fax: +82-02-588-6828 macronix offces : singapore macronix pte. ltd . 1 marine parade central, #11-03 parkway centre, singapore 449408 tel: +65-6346-5505 fax: +65-6348-8096 macronix offces : europe macronix europe n.v. koningin astridlaan 59, bus 1 1780 wemmel belgium tel: +32-2-456-8020 fax: +32-2-456-8021 macronix offces : usa macronix america, inc. 680 north mccarthy blvd. milpitas, ca 95035, u.s.a. tel: +1-408-262-8887 fax: +1-408-262-8810 |
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